227-0116-00L VLSI 1: HDL Based Design for FPGAs
Semester | Autumn Semester 2022 |
Lecturers | F. K. Gürkaynak, L. Benini |
Periodicity | yearly recurring course |
Language of instruction | English |
Number | Title | Hours | Lecturers | ||||||||||||||||||||||
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227-0116-00 G | VLSI 1: HDL Based Design for FPGAs | 5 hrs |
| F. K. Gürkaynak, L. Benini |