227-0128-00L  Synthesis of Digital Circuits

SemesterSpring Semester 2023
LecturersL. Josipovic
Periodicityyearly recurring course
Language of instructionEnglish



Courses

NumberTitleHoursLecturers
227-0128-00 VSynthesis of Digital Circuits2 hrs
Wed13:15-15:00ETZ G 91 »
L. Josipovic
227-0128-00 USynthesis of Digital Circuits1 hrs
Wed15:15-16:00ETZ G 91 »
05.04.13:15-16:00HG E 1.1 »
31.05.10:15-12:00ETZ G 91 »
L. Josipovic

Catalogue data

AbstractThis course covers theoretical and practical aspects of hardware compilation and synthesis. It provides a comprehensive view into the design flow of digital circuits and presents algorithms, tools, and methods to generate digital circuits from high-level descriptions. It discusses recent advancements and current challenges of high-level synthesis for FPGAs.
ObjectiveThe goal of this course is to provide students with an in-depth understanding of the hardware design process and hardware compilation techniques. The students will learn how to differentiate software and hardware design models. They will be able to apply high-level synthesis concepts to design hardware from software specifications. They will be able to contrast various HLS methods, assess the area-performance tradeoffs of different HLS solutions, and identify challenges and limitations of current FPGA-oriented HLS approaches.
ContentThe course will cover the following topics:
- Hardware design flow and introduction to high-level synthesis (HLS)
- Static code analysis and optimization
- Classic HLS algorithms for scheduling (e.g., ASAP, ALAP, List scheduling)
- Classic HLS algorithms for sharing and binding (e.g., Left-edge algorithm)
- Pipelining and SDC modulo scheduling
- Polyhedral code analysis and optimization
- Applications of HLS for FPGAs
- Challenges of modern HLS for FPGAs
- Recent HLS advancements and alternative HLS approaches
The course will be divided into two main blocks. The first block will consist of classical lectures, accompanied by exercises. The second block will interleave lectures with: (1) practical work that will introduce students to a standard HLS flow for FPGAs and (2) student presentations of recent research topics on HLS and FPGA design.
Lecture notesLecture notes will be provided on the course website.
LiteratureLiterature will be provided on the course website.
Prerequisites / NoticeThe course requires a basic understanding of digital circuit design and computer architecture. A background in FPGA design is not required.

Performance assessment

Performance assessment information (valid until the course unit is held again)
Performance assessment as a semester course
ECTS credits4 credits
ExaminersL. Josipovic
Typegraded semester performance
Language of examinationEnglish
RepetitionRepetition only possible after re-enrolling for the course unit.
Additional information on mode of examinationThe grade is composed out of:
- a written midterm exam, covering the theoretical topics of the first course block
- individual practical assignments, graded based on the correctness of the produced results and an oral discussion of the solution
- paper review and presentation, graded based on review quality (e.g., clarity of the paper summary, critical analysis of its advantages and shortcomings), presentation quality (e.g., language, writing style), and oral discussion

Learning materials

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Only public learning materials are listed.

Groups

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Restrictions

There are no additional restrictions for the registration.

Offered in

ProgrammeSectionType
Electrical Engineering and Information Technology MasterRecommended SubjectsWInformation
Electrical Engineering and Information Technology MasterSpecialization CoursesWInformation