227-0147-00L VLSI II: Design of Very Large Scale Integration Circuits
|Semester||Spring Semester 2018|
|Lecturers||F. K. Gürkaynak, L. Benini|
|Periodicity||yearly recurring course|
|Language of instruction||English|
|227-0147-00 G||VLSI II: Design of Very Large Scale Integration Circuits|
Vorlesung: Di 13-15
Übungen: Mi 9-12
|F. K. Gürkaynak, L. Benini|
|Abstract||This second course in our VLSI series is concerned with how to turn digital circuit netlists into safe, testable and manufacturable mask layout, taking into account various parasitic effects. Low-power circuit design is another important topic. Economic aspects and management issues of VLSI projects round off the course.|
|Objective||Know how to design digital VLSI circuits that are safe, testable, durable, and make economic sense.|
|Content||The second course begins with a thorough discussion of various technical aspects at the circuit and layout level before moving on to economic issues of VLSI. Topics include: |
- The difficulties of finding fabrication defects in large VLSI chips.
- How to make integrated circuit testable (design for test).
- Synchronous clocking disciplines compared, clock skew, clock distribution, input/output timing.
- Synchronization and metastability.
- CMOS transistor-level circuits of gates, flip-flops and random access memories.
- Sinks of energy in CMOS circuits.
- Power estimation and low-power design.
- Current research in low-energy computing.
- Layout parasitics, interconnect delay, static timing analysis.
- Switching currents, ground bounce, IR-drop, power distribution.
- Floorplanning, chip assembly, packaging.
- Layout design at the mask level, physical design verification.
- Electromigration, electrostatic discharge, and latch-up.
- Models of industrial cooperation in microelectronics.
- The caveats of virtual components.
- The cost structures of ASIC development and manufacturing.
- Market requirements, decision criteria, and case studies.
- Yield models.
- Avenues to low-volume fabrication.
- Marketing considerations and case studies.
- Management of VLSI projects.
Exercises are concerned with back-end design (floorplanning, placement, routing, clock and power distribution, layout verification). Industrial CAD tools are being used.
|Lecture notes||H. Kaeslin: "Top-Down Digital VLSI Design, from Gate-Level Circuits to CMOS Fabrication", Lecture Notes Vol.2 , 2015.|
All written documents in English.
|Literature||H. Kaeslin: "Top-Down Digital VLSI Design, from Architectures to Gate-Level Circuits and FPGAs", Elsevier, 2014, ISBN 9780128007303.|
|Prerequisites / Notice||Highlight:|
Students are offered the opportunity to design a circuit of their own which then gets actually fabricated as a microchip! Students who elect to participate in this program register for a term project at the Integrated Systems Laboratory in parallel to attending the VLSI II course.
"VLSI I: from Architectures to Very Large Scale Integration Circuits and FPGAs" or equivalent knowledge.
|Performance assessment information (valid until the course unit is held again)|
|Performance assessment as a semester course|
|ECTS credits||6 credits|
|Examiners||F. K. Gürkaynak, L. Benini|
|Language of examination||English|
|Repetition||The performance assessment is offered every session. Repetition possible without re-enrolling for the course unit.|
|Mode of examination||oral 30 minutes|
|Additional information on mode of examination||For examinations, we accept German and English as language.|
|This information can be updated until the beginning of the semester; information on the examination timetable is binding.|
|Only public learning materials are listed.|
|No information on groups available.|
|There are no additional restrictions for the registration.|