227-0148-00L VLSI III: Test and Fabrication of VLSI Circuits
Semester | Herbstsemester 2017 |
Dozierende | L. Benini |
Periodizität | jährlich wiederkehrende Veranstaltung |
Lehrveranstaltung | Findet dieses Semester nicht statt. |
Lehrsprache | Englisch |
Lehrveranstaltungen
Nummer | Titel | Umfang | Dozierende | |
---|---|---|---|---|
227-0148-00 G | VLSI III: Test and Fabrication of VLSI Circuits Findet dieses Semester nicht statt. Findet ab Herbstsemester 2018 wieder statt. Übungen gemäss Einschreibeliste | 4 Std. | L. Benini |
Katalogdaten
Kurzbeschreibung | In this course, we will cover how modern microchips are fabricated, and we will focus on methods and tools to uncover fabrication defects, if any, in these microchips. As part of the exercises, students will get to work on an industrial 1 million dollar automated test equipment. |
Lernziel | Learn about modern IC manufacturing methodologies, understand the problem of IC testing. Cover the basic methods, algorithms and techniques to test circuits in an efficient way. Learn about practical aspects of IC testing and apply what you learn in class using a state-of-the art tester. |
Inhalt | In this course we will deal with modern integrated circuit (IC) manufacturing technology and cover topics such as: - Today's nanometer CMOS fabrication processes (HKMG). - Optical and post optical Photolithography. - Potential alternatives to CMOS technology and MOSFET devices. - Evolution paths for design methodology. - Industrial roadmaps for the future evolution of semiconductor technology (ITRS). If you want to earn money by selling ICs, you will have to deliver a product that will function properly with a very large probability. The main emphasis of the lecture will be discussing how this can be achieved. We will discuss fault models and practical techniques to improve testability of VLSI circuits. At the IIS we have a state-of-the-art automated test equipment (Advantest SoC V93000) that we will make available for in class exercises and projects. At the end of the lecture you will be able to design state-of-the art digital integrated circuits such as to make them testable and to use automatic test equipment (ATE) to carry out the actual testing. During the first weeks of the course there will be weekly practical exercises where you will work in groups of two. For the last 5 weeks of the class students will be able to choose a class project that can be: - The test of their own chip developed during a previous semester thesis - Developing new setups and measurement methods in C++ on the tester - Helping to debug problems encountered in previous microchips by IIS. Half of the oral exam will consist of a short presentation on this class project. |
Skript | Main course book: "Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits" by Michael L. Bushnell and Vishwani D. Agrawal, Springer, 2004. This book is available online within ETH through http://link.springer.com/book/10.1007%2Fb117406 |
Voraussetzungen / Besonderes | Although this is the third part in a series of lectures on VLSI design, you can follow this course even if you have not visited VLSI I and VLSI II lectures. An interest in integrated circuit design, and basic digital circuit knowledge is required though. Course website: https://iis-students.ee.ethz.ch/lectures/vlsi-iii/ |
Leistungskontrolle
Information zur Leistungskontrolle (gültig bis die Lerneinheit neu gelesen wird) | |
Leistungskontrolle als Semesterkurs | |
ECTS Kreditpunkte | 6 KP |
Prüfende | F. K. Gürkaynak, L. Benini |
Form | Sessionsprüfung |
Prüfungssprache | Englisch |
Repetition | Die Leistungskontrolle wird in jeder Session angeboten. Die Repetition ist ohne erneute Belegung der Lerneinheit möglich. |
Prüfungsmodus | mündlich 30 Minuten |
Zusatzinformation zum Prüfungsmodus | Oral examination can also be held in German |
Diese Angaben können noch zu Semesterbeginn aktualisiert werden; verbindlich sind die Angaben auf dem Prüfungsplan. |
Lernmaterialien
Hauptlink | Information |
Es werden nur die öffentlichen Lernmaterialien aufgeführt. |
Gruppen
Keine Informationen zu Gruppen vorhanden. |
Einschränkungen
Keine zusätzlichen Belegungseinschränkungen vorhanden. |