Hasan Hassan: Catalogue data in Spring Semester 2022 |
| Name | Dr. Hasan Hassan |
| Department | Information Technology and Electrical Engineering |
| Relationship | Lecturer |
| Number | Title | ECTS | Hours | Lecturers | |
|---|---|---|---|---|---|
| 227-0085-34L | Projects & Seminars: Exploring Future Memory Systems with RAMulator  Only for Electrical Engineering and Information Technology BSc. The course unit can only be taken once. Repeated enrollment in a later semester is not creditable. | 3 credits | 3P | H. Hassan | |
| Abstract | The category of "Laboratory Courses, Projects, Seminars" includes courses and laboratories in various formats designed to impart practical knowledge and skills. Moreover, these classes encourage independent experimentation and design, allow for explorative learning and teach the methodology of project work. | ||||
| Learning objective | DRAM is predominantly used to build the main memory systems of modern computing devices. Simulation-based experimental studies are key for understanding the complex interactions between DRAM and modern applications. Ramulator is an extensible DRAM simulator providing cycle-accurate performance models for a variety of commercial DRAM standards (e.g., DDR3/4, LPDDR3/4, GDDR5, HBM) and academic proposals. Ramulator has a modular design that enables easy integration of additional DRAM standards and mechanisms. Ramulator is written in C++11 and can be easily integrated to full-system simulators such as gem5. In this P&S, you will design new DRAM and memory controller mechanisms for improving overall system performance, energy consumption, and reliability. You will extend Ramulator with these new designs and evaluate their performance, energy consumption, and reliability using modern applications. This will be the right P&S for you if you would like to learn about the state-of-the-art memory controller and DRAM designs and their interaction with modern applications. This P&S will also enable you to hands-on simulate and understand the memory system behavior of modern workloads such as machine learning, graph analytics, genome analysis. Prerequisites of the course: - Digital Design and Computer Architecture (or equivalent course) - A good knowledge in C/C++ programming language. - Interest in making things efficient and solving problems. - Interest in understanding software development and hardware design, and their interactions. The course is conducted in English. Course website: https://safari.ethz.ch/projects_and_seminars/doku.php?id=ramulator | ||||
| 227-0085-35L | Projects & Seminars: Enabling Secure, Reliable and Fast Memory with Hands-On FPGA Experiments Only for Electrical Engineering and Information Technology BSc. The course unit can only be taken once. Repeated enrollment in a later semester is not creditable. | 3 credits | 3P | H. Hassan | |
| Abstract | The category of "Laboratory Courses, Projects, Seminars" includes courses and laboratories in various formats designed to impart practical knowledge and skills. Moreover, these classes encourage independent experimentation and design, allow for explorative learning and teach the methodology of project work. | ||||
| Learning objective | DRAM is predominantly used to build the main memory systems of modern computing devices. To improve the performance, reliability, and security of DRAM, it is critical to perform experimental characterization and analysis of existing cutting-edge DRAM chips. SoftMC is an FPGA-based DRAM testing infrastructure that enables the programmer to perform all low-level DRAM operations (i.e., DDR commands) in a cycle-accurate manner. SoftMC provides a simple and intuitive high-level programming interface (in C++) that completely hides the low-level details of the FPGA from programmers. Programmers implement test routines in C++, and the test routines automatically get translated into the low-level SoftMC memory controller operations in the FPGA. SoftMC developers write low-level hardware description language code to enable new and faster studies. In this P&S, you will have the chance to learn how DRAM is organized and operates in a low-level and gain practical experience in using SoftMC while developing SoftMC programs for new DRAM characterization studies related to performance, reliability and security. You may also improve the SoftMC infrastructure itself to enable new studies. And, who knows, you might discover new security vulnerabilities like RowHammer. This will be the right P&S for you if you are interested in DRAM technology and would like to learn more about it as well as FPGA technology and how it can be used for practical purposes such as understanding and mitigating RowHammer attacks, generating true random numbers, reducing memory latency, fingerprinting and identifying devices, and improving reliability. Prerequisites of the course: - Digital Design and Computer Architecture (or equivalent course) - Familiarity with FPGA programming - Interest in low-level hacking and memory - Interest in discovering why things do or do not work and solving problems The course is conducted in English. Course website: https://safari.ethz.ch/projects_and_seminars/doku.php?id=softmc | ||||