Oscar Castañeda Fernández: Catalogue data in Autumn Semester 2021

Name Dr. Oscar Castañeda Fernández
Rechn. Modellierung Nanostrukturen
ETH Zürich, ETZ J 61.1
Gloriastrasse 35
8092 Zürich
Telephone+41 44 632 03 32
DepartmentInformation Technology and Electrical Engineering

227-0147-10LVLSI 3: Full-Custom Digital Circuit Design Restricted registration - show details 6 credits2V + 3UC. Studer, O. Castañeda Fernández
AbstractThis third course in our VLSI series is concerned with full-custom digital integrated circuits. The goals are to learn how to design digital circuits on the schematic, layout, gate, and register-transfer levels. The use of state-of-the-art CAD software (Cadence Virtuoso) in order to simulate, optimize, and characterize digital circuits is another important topic of this course.
ObjectiveAt the end of this course you will
- understand how the main building blocks of state-of-the-art digital integrated circuits are designed
- be able to design and optimize digital integrated circuits on the schematic, layout, and gate levels
- be able to use standard industry software (Cadence Virtuoso) for drawing, simulating, and characterizing digital circuits
- understand the performance trade-offs between speed, area, and power consumption
ContentThe third VLSI course begins with the basics of metal-oxide-semiconductor (MOS) field-effect transistors (FETs) and moves up the stack towards logic gates and increasingly complex digital circuit structures. The topics of this course include:
• Nanometer MOSFETs
• Static and dynamic behavior of complementary MOS (CMOS) inverters
• CMOS gate design, sizing, and timing
• Full-custom standard-cell design
• Wire models and parasitics
• Latch and flip-flop circuits
• Gate-level timing analysis and optimization
• Static and dynamic power consumption; low-power techniques
• Alternative logic styles (dynamic logic, pass-transistor logic, etc.)
• Arithmetic and logic circuits
• Fixed-point and floating-point arithmetic
• Memory circuits (ROM, SRAM, and DRAM)
• In- and near-memory processing architectures
• Full-custom accelerator circuits for machine learning
The exercises are concerned with schematic entry, layout, and simulation of digital integrated circuits using a disciplined standard-cell-based approach with Cadence Virtuoso.
LiteratureN. H. E. Weste and D. M Harris, CMOS VLSI Design: A Circuits and Systems Perspective (4th Ed.), Addison-Wesley
Prerequisites / NoticeVLSI3 can be taken in parallel with “VLSI1: HDL based design for FPGAs” and is designed to complement the topics of this course. Basic analog circuit knowledge is required.