Oscar Castañeda Fernández: Catalogue data in Autumn Semester 2022 |
| Name | Dr. Oscar Castañeda Fernández |
| Address | Institut für Integrierte Systeme ETH Zürich, ETZ J 61.2 Gloriastrasse 35 8092 Zürich SWITZERLAND |
| Telephone | +41 44 632 03 32 |
| caoscar@ethz.ch | |
| URL | https://ofcastaneda.github.io |
| Department | Information Technology and Electrical Engineering |
| Relationship | Lecturer |
| Number | Title | ECTS | Hours | Lecturers | ||||||||||||||
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| 227-0147-10L | VLSI 3: Full-Custom Digital Circuit Design  | 6 credits | 2V + 3U | C. Studer, O. Castañeda Fernández | ||||||||||||||
| Abstract | This third course in our VLSI series is concerned with full-custom digital integrated circuits. The goals include learning the design of digital circuits on the schematic, layout, gate, and register-transfer levels. The use of state-of-the-art CAD software (Cadence Virtuoso) in order to simulate, optimize, and characterize digital circuits is another important topic of this course. | |||||||||||||||||
| Learning objective | At the end of this course, you will • understand the design of the main building blocks of state-of-the-art digital integrated circuits • be able to design and optimize digital integrated circuits on the schematic, layout, and gate levels • be able to use standard industry software (Cadence Virtuoso) for drawing, simulating, and characterizing digital circuits • understand the performance trade-offs between delay, area, and power consumption | |||||||||||||||||
| Content | The third VLSI course begins with the basics of metal-oxide-semiconductor (MOS) field-effect transistors (FETs) and moves up the stack towards logic gates and increasingly complex digital circuit structures. The topics of this course include: • Nanometer MOSFETs • Static and dynamic behavior of complementary MOS (CMOS) inverters • CMOS gate design, sizing, and timing • Full-custom standard-cell design • Wire models and parasitics • Latch and flip-flop circuits • Gate-level timing analysis and optimization • Static and dynamic power consumption; low-power techniques • Alternative logic styles (dynamic logic, pass-transistor logic, etc.) • Arithmetic and logic circuits • Fixed-point and floating-point arithmetic • Synchronous and asynchronous design principles • Memory circuits (ROM, SRAM, and DRAM) • In- and near-memory processing architectures • Full-custom accelerator circuits for machine learning The exercises are concerned with schematic entry, layout, and simulation of digital integrated circuits using a disciplined standard-cell-based approach with Cadence Virtuoso. | |||||||||||||||||
| Literature | N. H. E. Weste and D. M Harris, CMOS VLSI Design: A Circuits and Systems Perspective (4th Ed.), Addison-Wesley | |||||||||||||||||
| Prerequisites / Notice | VLSI 3 can be taken in parallel with “VLSI 1: HDL-based design for FPGAs” and is designed to complement the topics of this course. Basic analog circuit knowledge is required. | |||||||||||||||||
Competencies |
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