Luca Benini: Katalogdaten im Herbstsemester 2017

NameHerr Prof. Dr. Luca Benini
LehrgebietDigitale Integrierte Schaltungen und Systeme
Adresse
Institut für Integrierte Systeme
ETH Zürich, ETZ J 84
Gloriastrasse 35
8092 Zürich
SWITZERLAND
Telefon+41 44 632 66 64
E-Maillbenini@iis.ee.ethz.ch
DepartementInformationstechnologie und Elektrotechnik
BeziehungOrdentlicher Professor

NummerTitelECTSUmfangDozierende
227-0116-00LVLSI I: From Architectures to VLSI Circuits and FPGAs Information 6 KP5GF. K. Gürkaynak, L. Benini
KurzbeschreibungThis first course in a series that extends over three consecutive terms is concerned with tailoring algorithms and with devising high performance hardware architectures for their implementation as ASIC or with FPGAs. The focus is on front end design using HDLs and automatic synthesis for producing industrial-quality circuits.
LernzielUnderstand Very-Large-Scale Integrated Circuits (VLSI chips), Application-Specific Integrated Circuits (ASIC), and Field-Programmable Gate-Arrays (FPGA). Know their organization and be able to identify suitable application areas. Become fluent in front-end design from architectural conception to gate-level netlists. How to model digital circuits with VHDL or SystemVerilog. How to ensure they behave as expected with the aid of simulation, testbenches, and assertions. How to take advantage of automatic synthesis tools to produce industrial-quality VLSI and FPGA circuits. Gain practical experience with the hardware description language VHDL and with industrial Electronic Design Automation (EDA) tools.
InhaltThis course is concerned with system-level issues of VLSI design and FPGA implementations. Topics include:
- Overview on design methodologies and fabrication depths.
- Levels of abstraction for circuit modeling.
- Organization and configuration of commercial field-programmable components.
- VLSI and FPGA design flows.
- Dedicated and general purpose architectures compared.
- How to obtain an architecture for a given processing algorithm.
- Meeting throughput, area, and power goals by way of architectural transformations.
- Hardware Description Languages (HDL) and the underlying concepts.
- VHDL and SystemVerilog compared.
- VHDL (IEEE standard 1076) for simulation and synthesis.
- A suitable nine-valued logic system (IEEE standard 1164).
- Register Transfer Level (RTL) synthesis and its limitations.
- Building blocks of digital VLSI circuits.
- Functional verification techniques and their limitations.
- Modular and largely reusable testbenches.
- Assertion-based verification.
- Synchronous versus asynchronous circuits.
- The case for synchronous circuits.
- Periodic events and the Anceau diagram.
- Case studies, ASICs compared to microprocessors, DSPs, and FPGAs.

During the exercises, students learn how to model digital ICs with VHDL. They write testbenches for simulation purposes and synthesize gate-level netlists for VLSI chips and FPGAs. Commercial EDA software by leading vendors is being used throughout.
SkriptTextbook and all further documents in English.
LiteraturH. Kaeslin: "Top-Down Digital VLSI Design, from Architectures to Gate-Level Circuits and FPGAs", Elsevier, 2014, ISBN 9780128007303.
Voraussetzungen / BesonderesPrerequisites:
Basics of digital circuits.

Examination:
In written form following the course semester (spring term). Problems are given in English, answers will be accepted in either English oder German.

Further details:
https://iis-students.ee.ethz.ch/lectures/vlsi-i/
227-0147-00LVLSI II: Design of Very Large Scale Integration Circuits Information
Findet dieses Semester nicht statt.
6 KP5GL. Benini
KurzbeschreibungDiese weiterführende Lehrveranstaltung in der Reihe VLSI behandelt alle Aspekte des Entwurfs digitaler ASICs von der Netzliste bis zum fertigen Layout unter Berücksichtigung diverser parasitärer Effekte. Besondere Aufmerksamkeit gilt dabei den Aspekten Funktionssicherheit, Testbarkeit und Energieeffizienz. Die Themen Wirtschaftlichkeit und Leitung von VLSI Projekten runden den Kurs ab.
LernzielDigitale VLSI-Schaltungen zu entwerfen wissen, welche funktionssicher, testbar, langlebig, und wirtschaftlich sinnvoll sind.
InhaltDiese weiterführende Lehrveranstaltung behandelt sowohl technische Aspekte auf Schaltungs- und Layout-Niveau als auch ökonomische Fragen hochintegrierter Schaltungen. Behandelt werden:
- Grundzüge des Prüfens hochintegrierter Schaltungen auf Fabrikationsdefekte.
- Testgerechter Schaltungsentwurf (Design for Test).
- Synchrone Taktungsdisziplinen im Vergleich, Clock Skew, Taktverteilung, Input/Output Timing.
- Synchronisation und Metastabilität.
- Schaltungstechnik von CMOS Gattern, Flip-Flops und RAM Speichern auf Transistorniveau.
- Wozu benötigen CMOS Schaltungen überhaupt Energie?
- Leistungsabschätzung und Low-Power Design.
- Forschungsrichtungen für energieeffizienteres Rechnen.
- Layoutbedingte parasitäre Effekte, Leitungsverzögerung, statische Timing Analyse.
- Schaltströme, induktiv sowie resistiv bedingte Spannungsabfälle, Speisungsverteilung.
- Floorplanning, Chip Assembly, Packaging.
- Layout-Entwurf auf Masken-Niveau, Layoutverifikation.
- Elektromigration, ESD und Latch-up.
- Formen der industriellen Zusammenarbeit in der Mikroelektronik.
- Worauf man beim Einsatz Virtueller Komponenten achten muss.
- Kostenstrukturen der ASIC Entwicklung und Herstellung.
- Anforderungen der Märkte, Entscheidungskriterien sowie Fallbeispiele.
- Ausbeutemodelle.
- Wege zur Fabrikation kleiner Stückzahlen.
- Marktüberlegungen mit Fallbeispielen.
- Leitung von VLSI Projekten.

Die Übungen führen durch den physischen Entwurf (Floorplanning, Plazierung, Verdrahtung, Takt- und Speisungsverteilung, Layoutverifikation) bis zu den verifizierten GDS II Fabrikationsdaten. Dabei gelangen industrielle CAD-Tools zum Einsatz.
SkriptH. Kaeslin: "Top-Down Digital VLSI Design, from Gate-Level Circuits to CMOS Fabrication", Lecture Notes Vol.2, 2015.

Sämtliche Unterlagen in englischer Sprache.
LiteraturH. Kaeslin: "Top-Down Digital VLSI Design, from Architectures to Gate-Level Circuits and FPGAs", Elsevier, 2014, ISBN 9780128007303.
Voraussetzungen / BesonderesHighlight:
Es wird die Möglichkeit geboten einen Chip nach eigenen Ideen zu entwickeln, welcher anschliessend tatsächlich fabriziert wird! Ein solches Projekt wird in Form einer Semesterarbeit am Institut für Integrierte Systeme parallel zum Besuch von VLSI II durchgeführt.

Voraussetzungen:
"VLSI I: von Architektur zu hochintegrierter Schaltung und FPGA" oder gleichwertige Kenntnisse.

Weiterführende Informationen:
https://iis-students.ee.ethz.ch/lectures/vlsi-ii/
227-0148-00LVLSI III: Test and Fabrication of VLSI Circuits Information
Findet dieses Semester nicht statt.
6 KP4GL. Benini
KurzbeschreibungIn this course, we will cover how modern microchips are fabricated, and we will focus on methods and tools to uncover fabrication defects, if any, in these microchips. As part of the exercises, students will get to work on an industrial 1 million dollar automated test equipment.
LernzielLearn about modern IC manufacturing methodologies, understand the problem of IC testing. Cover the basic methods, algorithms and techniques to test circuits in an efficient way. Learn about practical aspects of IC testing and apply what you learn in class using a state-of-the art tester.
InhaltIn this course we will deal with modern integrated circuit (IC) manufacturing technology and cover topics such as:
- Today's nanometer CMOS fabrication processes (HKMG).
- Optical and post optical Photolithography.
- Potential alternatives to CMOS technology and MOSFET devices.
- Evolution paths for design methodology.
- Industrial roadmaps for the future evolution of semiconductor technology (ITRS).

If you want to earn money by selling ICs, you will have to deliver a product that will function properly with a very large probability. The main emphasis of the lecture will be discussing how this can be achieved. We will discuss fault models and practical techniques to improve testability of VLSI circuits. At the IIS we have a state-of-the-art automated test equipment (Advantest SoC V93000) that we will make available for in class exercises and projects. At the end of the lecture you will be able to design state-of-the art digital integrated circuits such as to make them testable and to use automatic test equipment (ATE) to carry out the actual testing.

During the first weeks of the course there will be weekly practical exercises where you will work in groups of two. For the last 5 weeks of the class students will be able to choose a class project that can be:
- The test of their own chip developed during a previous semester thesis
- Developing new setups and measurement methods in C++ on the tester
- Helping to debug problems encountered in previous microchips by IIS.

Half of the oral exam will consist of a short presentation on this class project.
SkriptMain course book: "Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits" by Michael L. Bushnell and Vishwani D. Agrawal, Springer, 2004. This book is available online within ETH through
http://link.springer.com/book/10.1007%2Fb117406
Voraussetzungen / BesonderesAlthough this is the third part in a series of lectures on VLSI design, you can follow this course even if you have not visited VLSI I and VLSI II lectures. An interest in integrated circuit design, and basic digital circuit knowledge is required though.

Course website:
https://iis-students.ee.ethz.ch/lectures/vlsi-iii/