Luca Benini: Catalogue data in Spring Semester 2023

Name Prof. Dr. Luca Benini
FieldDigital Integrated Circuits and Systems
Institut für Integrierte Systeme
ETH Zürich, ETZ J 84
Gloriastrasse 35
8092 Zürich
Telephone+41 44 632 66 64
DepartmentInformation Technology and Electrical Engineering
RelationshipFull Professor

227-0085-16LProjects & Seminars: Machine Learning for Brain-Computer Interfaces Restricted registration - show details
Does not take place this semester.
The course unit can only be taken once. Repeated enrollment in a later semester is not creditable.
3 credits3PL. Benini
AbstractThe category of "Laboratory Courses, Projects, Seminars" includes courses and laboratories in various formats designed to impart practical knowledge and skills. Moreover, these classes encourage independent experimentation and design, allow for explorative learning and teach the methodology of project work.
ObjectiveA brain-computer interface (BCI) provides a communication and control channel based on the recognition of subject’s intention from spatiotemporal activity of the brain. A typical method to acquire neural activity signals is electroencephalograhy (EEG), which is often used in BCI. In order to make these data usable and get useful information out of them, signal processing techniques play a crucial role. Moreover, feature extraction and machine learning methods are applied to obtain a highly accurate BCI.
The aim of the Project and Seminars course is to give insights of signal processing and machine learning applied to brain-computer interfaces to undergraduate students, by having hands-on experience in brain signal acquisition, data processing, feature extraction, and machine learning.
227-0147-00LVLSI 2: From Netlist to Complete System on Chip Information 6 credits5GF. K. Gürkaynak, L. Benini
AbstractThis second course in our VLSI series is concerned with how to turn digital circuit netlists into safe, testable and manufacturable mask layout, taking into account various parasitic effects. Low-power circuit design is another important topic. Economic aspects and management issues of VLSI projects round off the course.
ObjectiveKnow how to design digital VLSI circuits that are safe, testable, durable, and make economic sense.
ContentThe second course begins with a thorough discussion of various technical aspects at the circuit and layout level before moving on to economic issues of VLSI. Topics include:
- The difficulties of finding fabrication defects in large VLSI chips.
- How to make integrated circuit testable (design for test).
- Synchronous clocking disciplines compared, clock skew, clock distribution, input/output timing.
- Synchronization and metastability.
- CMOS transistor-level circuits of gates, flip-flops and random access memories.
- Sinks of energy in CMOS circuits.
- Power estimation and low-power design.
- Current research in low-energy computing.
- Layout parasitics, interconnect delay, static timing analysis.
- Switching currents, ground bounce, IR-drop, power distribution.
- Floorplanning, chip assembly, packaging.
- Layout design at the mask level, physical design verification.
- Electromigration, electrostatic discharge, and latch-up.
- Models of industrial cooperation in microelectronics.
- The caveats of virtual components.
- The cost structures of ASIC development and manufacturing.
- Market requirements, decision criteria, and case studies.
- Yield models.
- Avenues to low-volume fabrication.
- Marketing considerations and case studies.
- Management of VLSI projects.

Exercises are concerned with back-end design (floorplanning, placement, routing, clock and power distribution, layout verification). Industrial CAD tools are being used.
Lecture notesH. Kaeslin: "Top-Down Digital VLSI Design, from Gate-Level Circuits to CMOS Fabrication", Lecture Notes Vol.2 , 2015.

All written documents in English.
LiteratureH. Kaeslin: "Top-Down Digital VLSI Design, from Architectures to Gate-Level Circuits and FPGAs", Elsevier, 2014, ISBN 9780128007303.
Prerequisites / NoticeHighlight:
Students are offered the opportunity to design a circuit of their own which then gets actually fabricated as a microchip! Students who elect to participate in this program register for a term project at the Integrated Systems Laboratory in parallel to attending the VLSI II course.

"VLSI I: from Architectures to Very Large Scale Integration Circuits and FPGAs" or equivalent knowledge.

Further details:
227-0148-00LVLSI 4: Practical VLSI: Measurement and Testing Information 6 credits4GF. K. Gürkaynak, L. Benini
AbstractIn this revamped course, we will concentrate on practical aspects of modern integrated circuit testing with an emphasis on hands-on-experience on an IC tester. This will help students to better understand several aspects that have been highlighted in previous VLSI lecture series and allow them to test their own ICs designed during prior semester/bachelor theses.
ObjectiveIn this course, students will:
- Get hands-on experience working in a modern IC Test laboratory and learn the steps needed to bring-up, characterize and test digital integrated circuits.
- Develop problem solving skills and get experience in approaching issues that involve many different engineering steps.
- Gather first hand experience how Design-For-Test (DFT) methodologies help for IC Design, and understand the trade-offs between performance and testability.
- Learn about challenges of IC Manufacturing process, and what kind of failures can be encountered, and get a deeper understanding of IC Design process
- For students that have worked on a prior bachelor/semester thesis on an IC design project, allow them to test their own IC.
ContentIf you want to earn money by selling ICs, you will have to deliver a product that will function properly with a very large probability. This lecture will be discussing how this can be achieved.

The main point of emphasis will be hands-on-exercises on a state-of-the-art automated test equipment (Advantest SoC V93000) where students will work in groups of two (or maximum three). Students will be able to schedule their exercises so that it fits their individual schedule.

There will also be concentrated classroom lectures that will convey the necessary information that students will need for the exercises which will cover aspects of
- Economics of testing
- CMOS manufacturing and fault models, stuck at faults
- Automated Test Equipment
- Measuring timing and power
- Testing of memories
- Built in Self-Test (BIST)

There will be 10 lectures (some weeks will be lecture free, exact schedule to be communicated) and 8 exercises. The final exercise will involve individual work where students test an IC with the knowledge they gained from previous exercises. Students that complete this exercise and present a test report (4-10 pages) will pass the course.

Please note that the exercises in this class are involved and will require you to make preparations in advance. Expect to spend at least 4 hours of your own time for exercise preparations, and expect at least three individual half day sessions for the final exercise where you test the IC to qualify for a passing grade. It will be possible to finish the exercises until the end of July.
Lecture notesThe following book will accompany students during the lecture: "Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits" by Michael L. Bushnell and Vishwani D. Agrawal, Springer, 2004. This book is available online within ETH through
LiteratureCourse website:
Prerequisites / NoticeVLSI4 is meant for students interested in digital IC Design and especially for students that are planning or have already done a bachelor/semester thesis on IC Design.

Although not strictly necessary, VLSI2 would be quite helpful for students visiting this lecture, VLSI2 and VLSI4 can be visited at the same time.

Other lectures of the VLSI series (VLSI1, VLSI3) are not needed to follow VLSI4.

Course website for up to date information:
227-0150-00LSystems-on-Chip for Data Analytics and Machine Learning6 credits4GL. Benini
AbstractSystems-on-chip architecture and related design issues with a focus on machine learning and data analytics applications. It will cover multi-cores, many-cores, vector engines, GP-GPUs, application-specific processors and heterogeneous compute accelerators. Special emphasis given to energy-efficiency issues and hardware-software techniques for power and energy minimization.
ObjectiveGive in-depth understanding of the links and dependencies between architectures and their energy-efficient implementation and to get a comprehensive exposure to state-of-the-art systems-on-chip platforms for machine learning and data analytics. Practical experience will also be gained through practical exercises and mini-projects (hardware and software) assigned on specific topics.
ContentThe course will cover advanced system-on-chip architectures, with an in-depth view on design challenges related to advanced silicon technology and state-of-the-art system integration options (nanometer silicon technology, novel storage devices, three-dimensional integration, advanced system packaging). The emphasis will be on programmable parallel architectures with application focus on machine learning and data analytics. The main SoC architectural families will be covered: namely, multi and many- cores, GPUs, vector accelerators, application-specific processors, heterogeneous platforms. The course will cover the complex design choices required to achieve scalability and energy proportionality. The course will will also delve into system design, touching on hardware-software tradeoffs and full-system analysis and optimization taking into account non-functional constraints and quality metrics, such as power consumption, thermal dissipation, reliability and variability. The application focus will be on machine learning both in the cloud and at the edges (near-sensor analytics).
Lecture notesSlides will be provided to accompany lectures. Pointers to scientific literature will be given. Exercise scripts and tutorials will be provided.
LiteratureJohn L. Hennessy, David A. Patterson, Computer Architecture: A Quantitative Approach (The Morgan Kaufmann Series in Computer Architecture and Design) 6th Edition, 2017.
Prerequisites / NoticeKnowledge of digital design at the level of "Design of Digital Circuits SS12" is required.

Knowledge of basic VLSI design at the level of "VLSI I: Architectures of VLSI Circuits" is required
227-0155-00LMachine Learning on Microcontrollers Restricted registration - show details
Registration in this class requires the permission of the instructors.
6 credits4GM. Magno, L. Benini
AbstractMachine Learning (ML) and artificial intelligence are pervading the digital society. Today, even low power embedded systems are incorporating ML, becoming increasingly “smart”. This lecture gives an overview of ML methods and algorithms to process and extracts useful near-sensor information in end-nodes of the “internet-of-things”, using low-power microcontrollers (ARM-Cortex-M; RISC-V).
ObjectiveLearn how to Process data from sensors and how to extract useful information with low power microprocessors using ML techniques. We will analyze data coming from real low-power sensors (accelerometers, microphones, ExG bio-signals, cameras…). The main objective is to study in detail how Machine Learning algorithms can be adapted to the performance constraints and limited resources of low-power microcontrollers becoming Tiny Machine learning algorithms.
ContentThe final goal of the course is a deep understanding of machine learning and its practical implementation on single- and multi-core microcontrollers, coupled with performance and energy efficiency analysis and optimization. The main topics of the course include:

- Sensors and sensor data acquisition with low power embedded systems

- Machine Learning: Overview of supervised and unsupervised learning and in particular supervised learning ( Decision Trees, Random, Support Vector Machines, Artificial Neural Networks, Deep Learning, and Convolutional Networks)

- Low-power embedded systems and their architecture. Low Power microcontrollers (ARM-Cortex M) and RISC-V-based Parallel Ultra Low Power (PULP) systems-on-chip.

- Low power smart sensor system design: hardware-software tradeoffs, analysis, and optimization. Implementation and performance evaluation of ML in battery-operated embedded systems.

The laboratory exercised will show how to address concrete design problems, like motion, gesture recognition, emotion detection, image, and sound classification, using real sensors data and real MCU boards.

Presentations from Ph.D. students and the visit to the Digital Circuits and Systems Group will introduce current research topics and international research projects.
Lecture notesScript and exercise sheets. Books will be suggested during the course.
Prerequisites / NoticePrerequisites: Good experience in C language programming. Microprocessors and computer architecture. Basics of Digital Signal Processing. Some exposure to machine learning concepts is also desirable.