Luca Benini: Katalogdaten im Herbstsemester 2022 |
| Name | Herr Prof. Dr. Luca Benini |
| Lehrgebiet | Digitale Integrierte Schaltungen und Systeme |
| Adresse | Institut für Integrierte Systeme ETH Zürich, ETZ J 84 Gloriastrasse 35 8092 Zürich SWITZERLAND |
| Telefon | +41 44 632 66 64 |
| lbenini@iis.ee.ethz.ch | |
| Departement | Informationstechnologie und Elektrotechnik |
| Beziehung | Ordentlicher Professor |
| Nummer | Titel | ECTS | Umfang | Dozierende | |
|---|---|---|---|---|---|
| 227-0085-16L | Projekte & Seminare: Machine Learning for Brain-Computer Interfaces  Nur für Elektrotechnik und Informationstechnologie BSc. Die Lerneinheit kann nur einmal belegt werden. Eine wiederholte Belegung in einem späteren Semester ist nicht anrechenbar. | 3 KP | 3P | L. Benini | |
| Kurzbeschreibung | Der Bereich Praktika, Projekte, Seminare umfasst Lehrveranstaltungen in unterschiedlichen Formaten zum Erwerb von praktischen Kenntnissen und Fertigkeiten. Ausserdem soll selbstständiges Experimentieren und Gestalten gefördert, exploratives Lernen ermöglicht und die Methodik von Projektarbeiten vermittelt werden. | ||||
| Lernziel | A brain-computer interface (BCI) provides a communication and control channel based on the recognition of subject’s intention from spatiotemporal activity of the brain. A typical method to acquire neural activity signals is electroencephalograhy (EEG), which is often used in BCI. In order to make these data usable and get useful information out of them, signal processing techniques play a crucial role. Moreover, feature extraction and machine learning methods are applied to obtain a highly accurate BCI. The aim of the Project and Seminars course is to give insights of signal processing and machine learning applied to brain-computer interfaces to undergraduate students, by having hands-on experience in brain signal acquisition, data processing, feature extraction, and machine learning. | ||||
| 227-0116-00L | VLSI 1: HDL Based Design for FPGAs  | 6 KP | 5G | F. K. Gürkaynak, L. Benini | |
| Kurzbeschreibung | This first course in a series that extends over three consecutive terms is concerned with tailoring algorithms and with devising high performance hardware architectures for their implementation as ASIC or with FPGAs. The focus is on front end design using HDLs and automatic synthesis for producing industrial-quality circuits. | ||||
| Lernziel | Understand Very-Large-Scale Integrated Circuits (VLSI chips), Application-Specific Integrated Circuits (ASIC), and Field-Programmable Gate-Arrays (FPGA). Know their organization and be able to identify suitable application areas. Become fluent in front-end design from architectural conception to gate-level netlists. How to model digital circuits with SystemVerilog. How to ensure they behave as expected with the aid of simulation, testbenches, and assertions. How to take advantage of automatic synthesis tools to produce industrial-quality VLSI and FPGA circuits. Gain practical experience with the hardware description language SystemVerilog and with industrial Electronic Design Automation (EDA) tools. | ||||
| Inhalt | This course is concerned with system-level issues of VLSI design and FPGA implementations. Topics include: - Overview on design methodologies and fabrication depths. - Levels of abstraction for circuit modeling. - Organization and configuration of commercial field-programmable components. - FPGA design flows. - Dedicated and general purpose architectures compared. - How to obtain an architecture for a given processing algorithm. - Meeting throughput, area, and power goals by way of architectural transformations. - Hardware Description Languages (HDL) and the underlying concepts. - SystemVerilog - Register Transfer Level (RTL) synthesis and its limitations. - Building blocks of digital VLSI circuits. - Functional verification techniques and their limitations. - Modular and largely reusable testbenches. - Assertion-based verification. - Synchronous versus asynchronous circuits. - The case for synchronous circuits. - Periodic events and the Anceau diagram. - Case studies, ASICs compared to microprocessors, DSPs, and FPGAs. During the exercises, students learn how to model FPGAs with SystemVerilog. They write testbenches for simulation purposes and synthesize gate-level netlists for FPGAs. Commercial EDA software by leading vendors is being used throughout. | ||||
| Skript | Textbook and all further documents in English. | ||||
| Literatur | H. Kaeslin: "Top-Down Digital VLSI Design, from Architectures to Gate-Level Circuits and FPGAs", Elsevier, 2014, ISBN 9780128007303. | ||||
| Voraussetzungen / Besonderes | Prerequisites: Basics of digital circuits. Examination: In written form following the course semester (spring term). Problems are given in English, answers will be accepted in either English oder German. Further details: https://iis-students.ee.ethz.ch/lectures/vlsi-i/ | ||||
| 227-0155-00L | Machine Learning on Microcontrollers Registration in this class requires the permission of the instructors. Class size will be limited to 25. Preference is given to students in the MSc EEIT. | 6 KP | 4G | M. Magno, L. Benini | |
| Kurzbeschreibung | Machine Learning (ML) and artificial intelligence are pervading the digital society. Today, even low power embedded systems are incorporating ML, becoming increasingly “smart”. This lecture gives an overview of ML methods and algorithms to process and extract useful near-sensor information in end-nodes of the “internet-of-things”, using low-power microcontrollers/ processors (ARM-Cortex-M; RISC-V) | ||||
| Lernziel | Learn how to Process data from sensors and how to extract useful information with low power microprocessors using ML techniques. We will analyze data coming from real low-power sensors (accelerometers, microphones, ExG bio-signals, cameras…). The main objective is to study in details how Machine Learning algorithms can be adapted to the performance constraints and limited resources of low-power microcontrollers. | ||||
| Inhalt | The final goal of the course is a deep understanding of machine learning and its practical implementation on single- and multi-core microcontrollers, coupled with performance and energy efficiency analysis and optimization. The main topics of the course include: - Sensors and sensor data acquisition with low power embedded systems - Machine Learning: Overview of supervised and unsupervised learning and in particular supervised learning (Bayes Decision Theory, Decision Trees, Random Forests, kNN-Methods, Support Vector Machines, Convolutional Networks and Deep Learning) - Low-power embedded systems and their architecture. Low Power microcontrollers (ARM-Cortex M) and RISC-V-based Parallel Ultra Low Power (PULP) systems-on-chip. - Low power smart sensor system design: hardware-software tradeoffs, analysis, and optimization. Implementation and performance evaluation of ML in battery-operated embedded systems. The laboratory exercised will show how to address concrete design problems, like motion, gesture recognition, emotion detection, image and sound classification, using real sensors data and real MCU boards. Presentations from Ph.D. students and the visit to the Digital Circuits and Systems Group will introduce current research topics and international research projects. | ||||
| Skript | Script and exercise sheets. Books will be suggested during the course. | ||||
| Voraussetzungen / Besonderes | Prerequisites: C language programming. Basics of Digital Signal Processing. Basics of processor and computer architecture. Some exposure to machine learning concepts is also desirable | ||||