Luca Benini: Catalogue data in Spring Semester 2020
|Prof. Dr. Luca Benini
|Digital Integrated Circuits and Systems
Institut für Integrierte Systeme
ETH Zürich, ETZ J 84
|+41 44 632 66 64
|Information Technology and Electrical Engineering
|VLSI II: Design of Very Large Scale Integration Circuits
|F. K. Gürkaynak, L. Benini
|This second course in our VLSI series is concerned with how to turn digital circuit netlists into safe, testable and manufacturable mask layout, taking into account various parasitic effects. Low-power circuit design is another important topic. Economic aspects and management issues of VLSI projects round off the course.
|Know how to design digital VLSI circuits that are safe, testable, durable, and make economic sense.
|The second course begins with a thorough discussion of various technical aspects at the circuit and layout level before moving on to economic issues of VLSI. Topics include:
- The difficulties of finding fabrication defects in large VLSI chips.
- How to make integrated circuit testable (design for test).
- Synchronous clocking disciplines compared, clock skew, clock distribution, input/output timing.
- Synchronization and metastability.
- CMOS transistor-level circuits of gates, flip-flops and random access memories.
- Sinks of energy in CMOS circuits.
- Power estimation and low-power design.
- Current research in low-energy computing.
- Layout parasitics, interconnect delay, static timing analysis.
- Switching currents, ground bounce, IR-drop, power distribution.
- Floorplanning, chip assembly, packaging.
- Layout design at the mask level, physical design verification.
- Electromigration, electrostatic discharge, and latch-up.
- Models of industrial cooperation in microelectronics.
- The caveats of virtual components.
- The cost structures of ASIC development and manufacturing.
- Market requirements, decision criteria, and case studies.
- Yield models.
- Avenues to low-volume fabrication.
- Marketing considerations and case studies.
- Management of VLSI projects.
Exercises are concerned with back-end design (floorplanning, placement, routing, clock and power distribution, layout verification). Industrial CAD tools are being used.
|H. Kaeslin: "Top-Down Digital VLSI Design, from Gate-Level Circuits to CMOS Fabrication", Lecture Notes Vol.2 , 2015.
All written documents in English.
|H. Kaeslin: "Top-Down Digital VLSI Design, from Architectures to Gate-Level Circuits and FPGAs", Elsevier, 2014, ISBN 9780128007303.
|Prerequisites / Notice
Students are offered the opportunity to design a circuit of their own which then gets actually fabricated as a microchip! Students who elect to participate in this program register for a term project at the Integrated Systems Laboratory in parallel to attending the VLSI II course.
"VLSI I: from Architectures to Very Large Scale Integration Circuits and FPGAs" or equivalent knowledge.
|Systems-on-chip for Data Analytics and Machine Learning
Previously "Energy-Efficient Parallel Computing Systems for Data Analytics"
|Systems-on-chip architecture and related design issues with a focus on machine learning and data analytics applications. It will cover multi-cores, many-cores, vector engines, GP-GPUs, application-specific processors and heterogeneous compute accelerators. Special emphasis given to energy-efficiency issues and hardware-software techniques for power and energy minimization.
|Give in-depth understanding of the links and dependencies between architectures and their energy-efficient implementation and to get a comprehensive exposure to state-of-the-art systems-on-chip platforms for machine learning and data analytics. Practical experience will also be gained through practical exercises and mini-projects (hardware and software) assigned on specific topics.
|The course will cover advanced system-on-chip architectures, with an in-depth view on design challenges related to advanced silicon technology and state-of-the-art system integration options (nanometer silicon technology, novel storage devices, three-dimensional integration, advanced system packaging). The emphasis will be on programmable parallel architectures with application focus on machine learning and data analytics. The main SoC architectural families will be covered: namely, multi and many- cores, GPUs, vector accelerators, application-specific processors, heterogeneous platforms. The course will cover the complex design choices required to achieve scalability and energy proportionality. The course will will also delve into system design, touching on hardware-software tradeoffs and full-system analysis and optimization taking into account non-functional constraints and quality metrics, such as power consumption, thermal dissipation, reliability and variability. The application focus will be on machine learning both in the cloud and at the edges (near-sensor analytics).
|Slides will be provided to accompany lectures. Pointers to scientific literature will be given. Exercise scripts and tutorials will be provided.
|John L. Hennessy, David A. Patterson, Computer Architecture: A Quantitative Approach (The Morgan Kaufmann Series in Computer Architecture and Design) 6th Edition, 2017.
|Prerequisites / Notice
|Knowledge of digital design at the level of "Design of Digital Circuits SS12" is required.
Knowledge of basic VLSI design at the level of "VLSI I: Architectures of VLSI Circuits" is required
|Machine Learning on Microcontrollers
Registration in this class requires the permission of the instructors. Class size will be limited to 30.
Preference is given to students in the MSc EEIT.
|3G + 2A
|M. Magno, L. Benini
|Machine Learning (ML) and artificial intelligence are pervading the digital society. Today, even low power embedded systems are incorporating ML, becoming increasingly “smart”. This lecture gives an overview of ML methods and algorithms to process and extract useful near-sensor information in end-nodes of the “internet-of-things”, using low-power microcontrollers/ processors (ARM-Cortex-M; RISC-V)
|Learn how to Process data from sensors and how to extract useful information with low power microprocessors using ML techniques. We will analyze data coming from real low-power sensors (accelerometers, microphones, ExG bio-signals, cameras…). The main objective is to study in details how Machine Learning algorithms can be adapted to the performance constraints and limited resources of low-power microcontrollers.
|The final goal of the course is a deep understanding of machine learning and its practical implementation on single- and multi-core microcontrollers, coupled with performance and energy efficiency analysis and optimization. The main topics of the course include:
- Sensors and sensor data acquisition with low power embedded systems
- Machine Learning: Overview of supervised and unsupervised learning and in particular supervised learning (Bayes Decision Theory, Decision Trees, Random Forests, kNN-Methods, Support Vector Machines, Convolutional Networks and Deep Learning)
- Low-power embedded systems and their architecture. Low Power microcontrollers (ARM-Cortex M) and RISC-V-based Parallel Ultra Low Power (PULP) systems-on-chip.
- Low power smart sensor system design: hardware-software tradeoffs, analysis, and optimization. Implementation and performance evaluation of ML in battery-operated embedded systems.
The laboratory exercised will show how to address concrete design problems, like motion, gesture recognition, emotion detection, image and sound classification, using real sensors data and real MCU boards.
Presentations from Ph.D. students and the visit to the Digital Circuits and Systems Group will introduce current research topics and international research projects.
|Script and exercise sheets. Books will be suggested during the course.
|Prerequisites / Notice
|Prerequisites: Good experience in C language programming. Microprocessors and computer architecture. Basics of Digital Signal Processing. Some exposure to machine learning concepts is also desirable.