Frank Kagan Gürkaynak: Catalogue data in Autumn Semester 2022 |  |
| Name | Mr Frank Kagan Gürkaynak |
| Address | Institut für Integrierte Systeme ETH Zürich, ETZ J 60.1 Gloriastrasse 35 8092 Zürich SWITZERLAND |
| Telephone | +41 44 632 27 26 |
| kgf@ethz.ch | |
| URL | http://www.iis.ee.ethz.ch/~kgf |
| Department | Information Technology and Electrical Engineering |
| Relationship | Lecturer |
| Number | Title | ECTS | Hours | Lecturers | |
|---|---|---|---|---|---|
| 227-0116-00L | VLSI 1: HDL Based Design for FPGAs  | 6 credits | 5G | F. K. Gürkaynak, L. Benini | |
| Abstract | This first course in a series that extends over three consecutive terms is concerned with tailoring algorithms and with devising high performance hardware architectures for their implementation as ASIC or with FPGAs. The focus is on front end design using HDLs and automatic synthesis for producing industrial-quality circuits. | ||||
| Learning objective | Understand Very-Large-Scale Integrated Circuits (VLSI chips), Application-Specific Integrated Circuits (ASIC), and Field-Programmable Gate-Arrays (FPGA). Know their organization and be able to identify suitable application areas. Become fluent in front-end design from architectural conception to gate-level netlists. How to model digital circuits with SystemVerilog. How to ensure they behave as expected with the aid of simulation, testbenches, and assertions. How to take advantage of automatic synthesis tools to produce industrial-quality VLSI and FPGA circuits. Gain practical experience with the hardware description language SystemVerilog and with industrial Electronic Design Automation (EDA) tools. | ||||
| Content | This course is concerned with system-level issues of VLSI design and FPGA implementations. Topics include: - Overview on design methodologies and fabrication depths. - Levels of abstraction for circuit modeling. - Organization and configuration of commercial field-programmable components. - FPGA design flows. - Dedicated and general purpose architectures compared. - How to obtain an architecture for a given processing algorithm. - Meeting throughput, area, and power goals by way of architectural transformations. - Hardware Description Languages (HDL) and the underlying concepts. - SystemVerilog - Register Transfer Level (RTL) synthesis and its limitations. - Building blocks of digital VLSI circuits. - Functional verification techniques and their limitations. - Modular and largely reusable testbenches. - Assertion-based verification. - Synchronous versus asynchronous circuits. - The case for synchronous circuits. - Periodic events and the Anceau diagram. - Case studies, ASICs compared to microprocessors, DSPs, and FPGAs. During the exercises, students learn how to model FPGAs with SystemVerilog. They write testbenches for simulation purposes and synthesize gate-level netlists for FPGAs. Commercial EDA software by leading vendors is being used throughout. | ||||
| Lecture notes | Textbook and all further documents in English. | ||||
| Literature | H. Kaeslin: "Top-Down Digital VLSI Design, from Architectures to Gate-Level Circuits and FPGAs", Elsevier, 2014, ISBN 9780128007303. | ||||
| Prerequisites / Notice | Prerequisites: Basics of digital circuits. Examination: In written form following the course semester (spring term). Problems are given in English, answers will be accepted in either English oder German. Further details: https://iis-students.ee.ethz.ch/lectures/vlsi-i/ | ||||