227-0116-00L VLSI 1: HDL based design for FPGAs
| Semester | Autumn Semester 2021 |
| Lecturers | F. K. Gürkaynak, L. Benini |
| Periodicity | yearly recurring course |
| Language of instruction | English |
| Number | Title | Hours | Lecturers | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 227-0116-00 G | VLSI 1: HDL based design for FPGAs | 5 hrs |
| F. K. Gürkaynak, L. Benini |